JTAG testing, also known as boundary-scan testing, refers to the testing of integrated circuit components and their interconnections through the use of a standardized serial test bus. In accordance with conventional JTAG architectures, JTAG components include internal circuitry dedicated to the JTAG function and four or five pins through which JTAG testers communicate with the components' JTAG circuitry. This internal circuitry includes a boundary-scan register and a test access port (TAP) controller. The boundary-scan register resides between the JTAG component's I/O pins and core logic circuits. Under the control of the TAP controller, the boundary-scan register may be substantially transparent to the normal operation of the JTAG component, may impress test vectors in lieu of logic states at the I/O pins and may sample logic states at the I/O pins. The boundary-scan registers of the various JTAG components within an electronic system are coupled together in series to make one long boundary-scan chain. A tester shifts out instructions and test vectors and shifts in control register contents and sampled test data through this boundary-scan chain.
Conventional JTAG test architectures fail to adequately manage and organize testing in many electronic systems and particularly in systems in which electronic components are arranged hierarchically. In hierarchically arranged systems, components are not independently or randomly interconnected. Rather, components are grouped together into modules, including hybrids, mother boards, daughter boards, other circuit boards, single in-line memory modules (SIMMs), multichip modules (MCMs) etc. Electronic systems are often constructed from an assortment of such modules.
The many benefits of modular construction include treating a single module as a unit rather than as a collection of individual components. Design, manufacturing and testing activities are all performed more quickly, more reliably and less expensively when a system is treated as a collection of a few modules rather than a collection of many components. However, conventional JTAG testing architectures fail to adequately support modular testing. In modular testing, testing is performed to a module level rather than to a component level. If a failure is detected in a module, then the entire module fails without regard to which components or interconnections within the module may be the cause of the module failure. Module-level testing is typically greatly simplified and much quicker than component-level testing for a given system. Simplification is highly desirable because it leads to quicker test design and debug along with more reliable test use.
Conventionally, JTAG components on modules are treated individually for testing purposes. Consequently, test vectors and circuitry descriptions become complex when the many individual JTAG components in a system are strung together. In addition, boundary-scan chains often become so long that serial data communication through the boundary-scan chains leads to slow test procedures. Increased reliability occurs because the signals internal to the module do not need to be accessed during testing in the higher-level assemblies. This is especially important when tri-state buffers share a common internal bus on the module. In this case, JTAG testing must ensure that multiple tri-state buffers with differing logic levels are not turned on simultaneously. By separating the internal and external boundary-scan paths, higher-level assemblies would not be manipulating the internal scan path, and would not be concerned with any potential damage to the module.
Furthermore, the requirement of including JTAG circuitry on many components of a module places an unnecessary burden on power consumption and the design task. If, for example, JTAG circuitry imposes an average 2000 gate burden on a JTAG component, then a component which cannot afford the 2000 gate burden due to a gate-limited design may be required to omit JTAG circuitry altogether. Moreover, if components are implemented using high power technologies, such as ECL, then the JTAG circuitry burden may cause power consumption to exceed acceptable levels.